POWER INTEGRITY FOR NANOSCALE INTEGRATED SYSTEMS

Description

Proven methods for noise-tolerant nanoscale integrated circuit design

This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7 processor illustrate real-world applications of the techniques presented in this practical resource.

Coverage includes:

• Significance of power integrity for integrated circuits
• Supply and substrate noise impact on circuits
• Clock generation and distribution with power integrity
• Signal and power integrity design for I/O circuits
• Power integrity degradation and modeling
• Lumped, distributed, and 3D modeling for power integrity
• Chip temperature and PI impact
• Low-power techniques and PI impact
• Power integrity case study using the IBM POWER7 processor chip
• Carbon nanotube interconnects for power delivery

Table of Contents 

Preface

Chapter 1 : Significance of Power Integrity for Integrated Circuits
Chapter 2 : Supply and Substrate Noise Impact on Circuits
Chapter 3 : Clock Generation and Clock Distribution with PI Degradation
Chapter 4 : Chip IO Circuits and PI
Chapter 5 : Modeling of Circuits and IP Cores for PI Analysis
Chapter 6 : Power Integrity Degradation and Modeling
Chapter 7 : Lowe Power Techniques and PI Impact
Chapter 8 : Chip Temperature and PI Impact
Chapter 9 : Case Study : Chip ZZZZZ, Inferences and Conclusions
Chapter 10 : PI in the Nanotechnology Realm